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SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
June 2009
FIN210AC 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
Features
Data & Control Bits Frequency Capability Interface Controller Usage Selectable Edge Rates Standby Current Core Voltage (VDDA/S) I/O Voltage (VDDP) ESD (I/O to GND) Package Ordering Information 10-bit 48MHz Camera or LCD Microcontroller, RGB, YUV m68 & i86 Yes <10A 2.8 to 3.6V 1.65 to 3.6V 15kV 32-Terminal MLP (Preliminary) 42-Ball USS-BGA FIN210ACMLX (Preliminary) FIN210ACGFX
Description
The FIN210AC SerDesTM is a low-power serializer / deserializer optimized for use in cell phone displays and camera paths. The device reduces a 10-bit data path to four wires. For camera applications, an additional master clock can be passed in the opposite direction of data flow. The device utilizes Fairchild's proprietary ultra-low power, lowEMI technology.
Applications
Slider, Folder, & Clamshell Mobile Handsets Printers Security Cameras
Related Resources
For samples and questions, please contact: Interface@fairchildsemi.com.
Typical Application
Internal Termination Built-in voltage translation
FIN210AC
+ -
FIN210AC
2 2
+ 10-Bit Serializer 12-Bit Serializer
Camera Module
10-Bit 12-Bit Des erializer
Baseband
+ -
+ -
CTLTM Isolates interface for signal integrity Up to 48MHz
Camera Module
Figure 1. Mobile Phone Example
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 www.fairchildsemi.com
SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
FIN210AC (Serializer DIRI=1) Pin Descriptions
Pin Name
DIRI CTL_ADJ S0 S1 PLL0 PLL1 CKREF STROBE DP[1:10] CKSO+ CKSODSO+ DSOCKSI+ CKSICKP /DIRO VDDP VDDS VDDA GND N/C
Description
Control to determine serializer or deserializer configuration. Adjusts CTL drive to compensate for environmental conditions and length. Configure frequency range for the PLL. Configure frequency range for the PLL. Divide or adjust the serial frequency. 0 Deserializer 1 Serializer 0 Low drive (low power) 1 High drive (high power) See Table 1 Serializer (DIRI=1) Control Pin. See Table 1 Serializer (DIRI=1) Control Pin. See Table 1 Serializer (DIRI=1) Control Pin.
Divide or adjust the serial frequency. See Table 1 Serializer (DIRI=1) Control Pin. LV-CMOS clock input and PLL reference. LV-CMOS strobe input for latching data (DP [1:12]) into the serializer on the rising edge. LV-CMOS parallel data input. (GND input if not used) CTL Differential serializer output bit clock. CKSO+: Positive signal; CKSO-: Negative signal. CTL Differential serial output data signals. DSO+: Positive signal; DSO-: Negative signal. CTL Differential deserializer input bit clock. No connect unless in "clock pass-through" mode. CKSI+: Positive signal; CKSI-: Negative signal. LV-CMOS word clock output or Pixel clock output. No connect unless in "clock pass-through" mode. LV-CMOS output, Inversion of DIRI in normal operation. Can be used to drive the DIRI No connect if not used. signal of the deserializer where the interface needs to be turned around. Power supply for parallel I/O. (All VDDP pins must be connected to VDDP) Power supply for serial I/O. Power supply for core. All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 29 & GND PAD must be grounded. No connect. (Do not connect to GND or VDD)
Note: 1. 0=GND; 1=VDDP
FIN210AC (Serializer DIRI=1) Pin Configurations
27 STROBE 26 CKREF
1 A B C D E F G
DP[4]
2
DP[2]
3
GND
4
CTL_ADJ
5
N/C
6
28 CTL_ADJ
CKREF
DP[6]
DP[5]
DP[1]
N/C
STROBE
/DIRO
29 GND
25 /DIRO
32 DP[3]
31 DP[2]
30 DP[1]
DP[4] 1
CKP N/C DP[3] N/C CKSO+ CKSO -
24 CKSO+ 23 CKSOSERIALIZER GND PAD 22 DSO+ 21 DSO20 CKSI19 CKSI+ 18 DIRI 17 VDDS
PLL0 13 GND 11 PLL1 12 S1 14 S0 15 DP[10] 9 VDDA 16
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DP[5] 2 DP[6] 3 VDDP 4 CKP 5 DP[7] 6 DP[8] 7 DP[9] 8
GND 10
N/C
DP[7]
VDDP
GND
DSO-
DSO+
DP[8]
DP[9]
GND
VDDS
CKSI+
CKSI-
DP[10]
GND
N/C
VDDA
N/C
DIRI
GND
N/C
PLL1
PLL0
S1
S0
42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View)
32-pin MLP, 5 x 5mm, .5mm pitch (Top View) (Center pad must be grounded)
Figure 2. FIN210AC (Serializer DIRI=1) Pin Assignments (Top View)
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 2
SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
FIN210AC (Deserializer DIRI=0) Pin Descriptions
Pin Name
DIRI XTERM S0 S1 PWS0 PWS1 /ENZ DP[1:10] CKP DSI+ DSICKSI+ CKSICKSO+ CKSOCKREF STROBE /DIRO VDDP VDDS VDDA GND N/C
Description
Control to determine serializer or deserializer configuration. Control to determine if using internal or external termination Signals used to define the edge rate of parallel I/O. Signals used to define the edge rate of parallel I/O. Configure CKP pulse width. Configure CKP pulse width. 0 Deserializer 1 Serializer 0 Internal termination used 1 External termination required on CKSI & DSI See Table 2 Deserializer (DIRI=0) Control Pin. See Table 2 Deserializer (DIRI=0) Control Pin. See Table 2 Deserializer (DIRI=0) Control Pin. See Table 2 Deserializer (DIRI=0) Control Pin.
High-Z or known state outputs during power down See Table 5 Deserializer (DIRI=0) Control Pin. LV-CMOS parallel data output. (N/C if not used) LV-CMOS word clock output or Pixel clock output. CTL Differential serial input data signals. DSI+: Positive signal; DSI-: Negative signal. CTL Differential deserializer input bit clock. CKSI+: Positive signal; CKSI-: Negative signal. CTL Differential serializer output bit clock. No connect unless in "clock pass-through" mode. CKSO+: Positive signal; CKSO-: Negative signal. LV-CMOS clock input and PLL reference. No connect unless in "clock pass-through" mode. LV-CMOS strobe input for latching data into the serializer. No connect unless in "clock pass-through" mode. LV-CMOS Output. Inversion of DIRI in normal operation. No connect if not used. Power supply for parallel I/O. (All VDDP pins must be connected to VDDP) Power supply for serial I/O. Power supply for core. All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 28, 29, GND PAD must be grounded. No connect. BGA: G1, F2; MLP: 10, 11; (Do not connect to GND or VDD)
Note: 2. 0=GND; 1=VDDP
FIN210AC (Deserializer DIRI=0) Pin Configurations
27 STROBE 29 XTRM 26 CKREF
1 A
DP[4]
2
DP[2]
3
XTRM
4
/ENZ
5
N/C
6
31 DP[2]
CKREF
B
DP[6]
DP[5]
DP[1]
N/C
STROBE
/DIRO
25 /DIRO
32 DP[3]
30 DP[1]
28 /ENZ
DP[4] 1
CKP N/C DP[3] N/C CKSO+ CKSO-
24 CKSO+ 23 CKSODESERIALIZER GND PAD 22 DSI21 DSI+ 20 CKSI19 CKSI+ 18 DIRI 17 VDDS
PWS0 13 N/C 11 PWS1 12 S1 14 S0 15 DP[10] 9 VDDA 16
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C
DP[5] 2 DP[6] 3 VDDP 4 CKP 5 DP[7] 6 DP[8] 7 DP[9] 8
N/C 10
D
N/C
DP[7]
VDDP
GND
DSI+
DSI-
E
DP[8]
DP[9]
GND
VDDS
CKSI+
CKSI-
F
DP[10]
N/C
N/C
VDDA
N/C
DIRI
G
N/C
N/C
PWS1
PWS0
S1
S0
42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View)
32-pin MLP, 5mm x 5mm, .5mm pitch (Top View) (Center pad must be grounded)
Figure 3. FIN210AC (Deserializer DIRI=0) Pin Assignments (Top View)
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 3
SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
System Control Pin
Table 1. Serializer (DIRI=1) Control Pin
Function Conditions CKREF STROBE Slow Frequencies Normal operation Supports spread spectrum on CKREF With a fixed CKREF input; STROBE can be 1/2 the speed With a fixed CKREF input; STROBE can be 1/3 the speed Normal operation Supports spread spectrum on CKREF With a fixed CKREF input; STROBE can be 1/2 the speed With a fixed CKREF input; STROBE can be 1/3 the speed Normal operation Supports spread spectrum on CKREF With a fixed CKREF input; STROBE can be 1/2 the speed With a fixed CKREF input; STROBE can be 1/3 the speed 5MHz to 15MHz 5MHz to 14.2MHz 5MHz to 15MHz 5MHz to 15MHz CKREF (Up to 15MHz) CKREF (Up to 14.2MHz) CKREF / 2 (Up to 7.5MHz) CKREF / 3 (Up to 5MHz) 1 0.947 2 3 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 PLL Multiplier PLL0 Control Pin PLL1 S0 S1
Medium Frequencies 10MHz to 30MHz 10MHz to 28.4MHz 10MHz to 30MHz 10MHz to 30MHz CKREF (Up to 30MHz) CKREF (Up to 28.4MHz) CKREF / 2 (Up to 15MHz) CKREF / 3 (Up to 10MHz) Fast Frequencies 18MHz to 48MHz 18MHz to 45.4MHz 18MHz to 48MHz 18MHz to 48MHz Power-Down CKREF (Up to 48MHz) CKREF (Up to 45.4MHz) CKREF / 2 (Up to 24MHz) CKREF / 3 (Up to 16MHz) 1 0.947 2 3 1 0 0 1 X 0 0 1 1 X 1 1 1 1 0 0 0 0 0 0 1 0.947 2 3 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1
Table 2.
Deserializer (DIRI=0) PWS Control Pins (Pulse Width Examples)
CKP Pulse Width Low Time CKREF=19.2 MHz CKREF=26 MHz CKREF=48 MHz Reference PLL Pwidth Multiplier Multiplier (Serializer) Control Pin PWS0 PWS1
CKP to STROBE
Serializer PLL Multiplier = 3 Non-Inverted Inverted Non-Inverted Non-Inverted Non-Inverted Inverted Non-Inverted Non-Inverted Non-Inverted Inverted Non-Inverted Non-Inverted 78.1ns 78.1ns 156.3ns 208.3ns 52.1ns 52.1ns 104.2ns 138.9ns 26ns 26ns 52.1ns 69.4ns Power-Down
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 4
57.7ns 57.7ns 115.4ns 153.8ns 38.5ns 38.5ns 76.9ns 102.6ns 19.2ns 19.2ns 38.5ns 51.3ns
31.2ns 31.2ns 62.5ns 83.3ns 20.8ns 20.8ns 41.7ns 55.6ns 10.4ns 10.4ns 20.8ns 27.8ns
3 3 3 3 2 2 2 2 1 1 1 1
X
6 6 12 16 6 6 12 16 6 6 12 16 X
0 1 0 1 0 1 0 1 0 1 0 1 0
0 0 1 1 0 0 1 1 0 0 1 1 0
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Serializer PLL Multiplier = 2
Serializer PLL Multiplier = 1
SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
Table 3.
Deserializer S0 & S1 Control Pins (Note: All edge rates are typical values)
LVCMOS Output Edge Rates S0
0 1 1 0
S1
1 1 0 0
Slow Edge Rates Medium Edge Rates Fast Edge Rates Power Down
~7 - 8ns (CL = 8pF) ~4 - 5ns (CL = 8pF) ~2 - 3ns (CL = 8pF)
Pulse Width Calculations
CKP Pulse Width Low Time=(PLL Multiplier * Pwidth Multiplier) / (CKREF*12) Example: CKREF=26MHz; PLL Multiplier=1; Pwidth Multiplier=6 CKP Pulse width=(1 * 6) / (26MHz * 12)=19.2ns (2) (1)
CKREF = Strobe 50% Duty Cycle
If CKREF = Strobe the below control states will provide a ~ 50% duty cycle pulse width output on CKP
Table 4.
CKREF = Strobe 50% Duty Cycle Serializer
PLL0 1 PLL1 0 PWS0 0
Deserializer
PWS1 0
Power-Down States
When both S1 and S0 signals are 0, regardless of the state of the DIRI signal, the FIN210AC resets and powers down. The power-down mode shuts down all internal analog circuitry, disables the serial input and output of the device, and resets all internal digital logic. Table 5 indicates the state of the input states and output buffers in Power-Down mode.
Table 5.
Power-Down DIRI=1 (Serializer)
Inputs Disabled HIGH Input Disabled Input Disabled 0
Signal Pins
DP[1:10] CKP STROBE CKREF /DIRO
DIRI=0 (Deserializer) /ENZ = 0
Outputs High-Z High-Z Input Disabled Input Disabled 1
DIRI=0 (Deserializer) /ENZ = 1
Outputs Low High Input Disabled Input Disabled 1
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 5
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SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
Clock Pass-Through Mode
Clock pass-through mode allows a harmonic rich clock source to be sent to the serializer in a CTL format to reduce the overall harmonic content of the phone, and can reduce the need for EMI filters. The Master Clock Pass through mode performs a translation to the clock in the CTL link, and does not serialize this signal. The following describes how to enable this functionality for an image sensor (See Figure 6). Deserializer Configuration (DIRI=0) 1. 2. 1. Connect CKREF(BGA pin A6) to GROUND Connect master clock to STROBE (BGA pin B5) CKSI passes master clock to CKP output (BGA pin C1)
Serializer Configuration (DIRI=1)
CKREF and STROBE Signals
Please note that there is a setup and hold time between STROBE and data that must be met as seen on the electrical characteristics section. The relationship between CKREF and STROBE can be synchronous or asynchronous depending on what is available in the system. It is suggested that if the signals are synchronous and in normal operation that CKREF is tied to STROBE as close to the chip as possible. If you are running an asynchronous or spread spectrum setup, please be aware this may result on cycle jitter on the CKP signal. They cycle jitter does not effect the output data and clock relationship, the display or end application should continue to work as normal.
PLL Note
Please note that the PLL ranges can overlap, power consumption can be reduced by selecting the operation in the lower end of the higher speed PLL range.
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 6
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SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
Application Diagrams
The following application diagrams illustrate the most typical applications for the FIN210 device. Specific configurations of the control pins may vary based on the needs of a given system. The following recommendations are valid for all of the applications shown.
FIN210AC Serializer VDDP1
D3 E4 F4
Baseband Processor PIXEL CLK NC Data[7:0] HSYNC VSYNC
A6 B5 C1
VDD
FIN210AC Deserializer VDDP2
E4 F4 D3
VDDP CKREF STROBE CKP DP[8:1] DP[9] DP[10]
VDDS/A CKSO+ C5 C6 CKSODSO+ D5 DSOD6 E5 E6 D5 D6
VDDS/A CKSI+ CKSIDSI+ DSI-
VDDP CKP C1 CKREF A6 B5 STROBE DP[8:1] E2 DP[9] F1 DP[10] A4 /ENZ
B3:E1
LCD MODULE PIXEL CLK
B3:E1 E2 F1
Data[7:0] HSYNC VSYNC
VDDP1
F6 G3 G4 A4 G5 G6
A3 NC NCC6 CKSOCKSIXTRM F6 E5 NC NCC5 CKSO+ DIRI CKSI+ DIRI G3 PLL1 PWS1 G4 B6 B6 NC NC /DIRO PLL0 /DIRO PWS0 CTL_ADJ G5 S1 S1 G6 S0 S0 GND GND
E6
/RES
/RES
Figure 4. 8-Bit RGB Application (Example Shows BGA 42-Pin Package)
Serializer Configuration: 10MHz to 30MHz Frequency Range (S1=S0=1) Normal Mode (PLL1=0; PLL0=1)
FIN210AC Dese rializer VDDP1
D3 E4 F4
Deserializer Configuration: ~4 - 5ns output edge rates (S1=S0=1) ~50% CKP PW,(PWS1=PWS0=0)
FIN210AC Serializer
E4 F4
Baseban d Processor
A6 B5 C1 B3:E1 E2 F1 A4 F6 G3 G4 A3 G5 G6
VDD
VDDP2
D3
VDDP CKREF STROBE CKP DP[8:1] DP[9] DP[10]
/ENZ
VDDS/A CKSO+ CKSODSI+ DSICKSICKSI+ /DIRO
C5 C6 D5 D6 E6 E5 B6 E5 E6 D6 D5 C6
VDDS/A CKSI+ CKSIDSO+ DSO-
VDDP CKP CKREF STROBE DP[8:1] DP[9] DP[10]
C1 A6 B5 B3:E1 E2 F1
Camera Module MASTER CLK PIXEL CLK YUV[7:0] HSYNC VSYNC /RES
MASTER CLK PIXEL CLK YUV[7:0] HSYNC VSYNC
CKSOC5 CKSO+ NC
B6
DIRI PWS1 PWS0 XTRM S1 S0
NC
/DIRO
GND
DIRI PLL1 PLL0 CTL_ADJ S1 S0 GND
F6 G3 G4 A4 G5 G6
VDDP2
/RES
Figure 5. 8-Bit YUV 1.3MPixel CMOS Imager (Example Shows BGA 42-Pin Package)
Deserializer Configuration: ~2 - 3ns output edge rates (S1=0, S0=1) ~50% CKP PW,(PWS1=PWS0=0) Serializer Configuration: 18MHz to 48MHz Frequency Range (S1=0, S0=1) Normal Mode (PLL1=0, PLL0=1)
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 7
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SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
Application Diagrams (Continued)
FIN210AC Dese rializer VDDP1
D3 E4 F4
Baseban d Processor
A6 B5 C1 B3:E1 E2 F1 A4 F6 G3 G4 A3 G5 G6
VDD
E4
FIN210AC Serializer
F4
VDDP2
D3
VDDP CKREF STROBE CKP DP[8:1] DP[9] DP[10]
/ENZ
VDDS/A CKSO+ CKSODSI+ DSICKSICKSI+ /DIRO
C5 C6 D5 D6 E6 E5 B6 E5 E6 D6 D5 C6
VDDS/A CKSI+ CKSIDSO+ DSO-
VDDP CKP CKREF STROBE DP[8:1] DP[9] DP[10]
C1 A6 B5 B3:E1 E2 F1
Camera Module MASTER CLK PIXEL CLK YUV[7:0] HSYNC VSYNC /RES
MASTER CLK PIXEL CLK YUV[7:0] HSYNC VSYNC
CKSOC5 CKSO+ NC
B6
DIRI PWS1 PWS0 XTRM S1 S0
NC
/DIRO
GND
DIRI PLL1 PLL0 CTL_ADJ S1 S0 GND
F6 G3 G4 A4 G5 G6
VDDP2
/RES
Figure 6. 8-Bit YUV 1.3MPixel CMOS Imager In Clock Pass-Through Mode
Serializer Configuration: 18MHz to 48MHz Frequency Range (S1=0, S0=1) Normal Mode (PLL1=0; PLL0=1) Master clock bypass mode. Deserializer Configuration: ~2 - 3ns output edge rates (S1=0, S0=1) ~50% CKP PW,(PWS1=PWS0=0)
Baseband Processor SYS CLK /WE NC Data[7:0] A0 /CS0
A6 B5 C1
FIN210AC Serializer VDDP1
D3 E4 F4
VDD
FIN210AC Deserializer VDDP2
E4 F4 D3
VDDP CKREF STROBE CKP DP[8:1] DP[9] DP[10]
VDDS/A CKSO+ C5 C6 CKSOD6 DSO+ D5 E5 E6 D5 D6
VDDS/A CKSI+ CKSIDSI+ DSI-
VDDP CKP C1 CKREF A6 B5 DP[8:1] E2 DP[9] F1 DP[10]
/ENZ
A4 A3 B3:E1
MAIN LCD /WE DATA[7:0] A0 /CS /RES
STROBE
B3:E1 E2 F1
DSO-
VDDP1
F6 G3 G4 A4 G5 G6
DIRI PLL1 PLL0 CTL_ADJ S1 S0 GND
E6 NC NCC6 CKSOCKSIE5 NC NCC5 CKSO+ CKSI+
/DIRO
B6
NC NC
B6
/DIRO
XTRM F6 DIRI G3 PWS1 G4 PWS0 S1 G6 S0
G5
GND
/RES
Figure 7. 8-Bit WRITE-Only Microcontroller Interface (Example Shows BGA 42-Pin Package)
Serializer Configuration: 18MHz to 48MHz Frequency Range (S1=0, S0=1) CKREF is twice as fast STROBE (PLL1=1; PLL0=0) CKREF=26MHz & STROBE Frequency=10 MHz Deserializer Configuration: ~7 - 8ns output edge rates (S1=1, S0=0) ~50% CKP PW,(PWS1=PWS0=0)
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 8
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SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
Additional Application Information
Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB. Keep all four differential Serial Wires the same length. Do not allow noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential serial wires. Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. Design goal of 100 differential characteristic impedance. Do not place test points on differential serial wires. Use differential serial wires a minimum of 2cm away from the antenna. For additional applications notes or flex guidelines see your sales representative or contact Fairchild directly. For samples and questions, please contact: Interface@fairchildsemi.com.
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 9
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SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol
VDD Supply Voltage All Input/Output Voltage CTL Output Short-Circuit Duration TSTG TJ TL Storage Temperature Range Maximum Junction Temperature Lead Temperature (Soldering, four seconds) Human Body Model JESD22-A114 ESD Charged Device Model, JESD22-C101 IEC61000-4-2 Serial I/O Pins to GND All Pins
Parameter
Min.
-0.5V -0.5 Continuous -65 +150 +260
Max.
+4.6 VDD+0.5 +150
Unit
V V C C C
12 8 2 15 kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol
VDDA, VDDS VDDP TA VDDA-PP Supply Voltage Supply Voltage Operating Temperature Supply Noise Voltage
Parameter
Min.
2.8 1.65 -30 100
Max.
3.6 3.60 +70
Unit
V V C mVPP
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 10
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SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
DC Electrical Characteristics
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol
LVCMOS I/O VIH VIL VOH Input High Voltage Input Low Voltage IOH=-2.0mA, S1=0,S0=1 Output High Voltage IOH=-0.4mA, S1=1,S0=0 IOH=-1.0mA, S1=1,S0=1 IOL=2.0mA, S1=0,S0=1 VOL IIN Output Low Voltage Input Current IOL=0.4mA, S1=1,S0=0 IOL=1.0mA, S1=1,S0=1 VIN= 0V to 3.6V CTL_ADJ=0 CTL_ADJ=1 CTL_ADJ=0 CTL_ADJ=1 VID=50mV, VIC=925mV DIRI=0 VID=50mV, VIC=925mV -5.0 -4.1 -5.3 2.1 3.1 0 80 80 100 100 120 120 5.0 A 0 0.25xVDDP V 0.75xVDDP VDDP V 0.65xVDDP GND VDDP 0.35xVDDP V
Parameter
Test Conditions
Min.
Typ.
(3)
Max.
Unit
DIFFERENTIAL I/O IODH IODL VGO RTRM Output HIGH Source Current Output LOW Sink Current Input Voltage Ground Offset(4) CKS Internal Receiver Termination Resistor DS Internal Receiver Termination Resistor VOS=1.0V VOS=1.0V mA mA V
DIRI=0
Notes: 3. Typical values are given for VDD=2.775V and TA=25C. Positive current values refer to the current flowing into the device and negative values refer to the current flowing out of pins. Voltages are referenced to GROUND unless otherwise specified (except VOD and VOD). 4. VGO is the difference in device ground levels between the CTL driver and the CTL receiver.
Power Supply Currents
Symbol IDD_PD Parameter VDD Power-Down Supply Current Test Conditions S1=S0=0, All Inputs at GND or VDD S1=L S0=H IDD_SER1 Dynamic Serializer Power Supply Current fCKREF=fSTRB, PLL1=0,PLL0=1; S1=H CTL_ADJ=0; CL=0pF S0=L S1=H S0=H S1=L S0=H IDD_DES1 Dynamic Deserializer Power Supply Current fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF S1=H S0=L S1=H S0=H 20MHz 48MHz 5MHz 14MHz 8MHz 28MHz 20MHz 48MHz 5MHz 14MHz 8MHz 28MHz Min. Typ. 0.1 13 21 10 16 11 18 10 19 8 9 9 12 Max. Unit A mA mA mA mA mA mA mA mA mA mA mA mA
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 11
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SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
Pin Capacitance Tables
Symbol
CIN, CIO, CIO-DIFF
Parameter
Capacitance of Input Only Signals; Parallel Port Pins DP[1:10]; Differential I/O
Test Conditions
DIRI=1, S1=0, S0=0, VDD=2.5V
Min.
Typ.
2
Max.
Unit
pF
AC Electrical Characteristics
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter Test Conditions
S1=0, S0=1 fCKREF=fSTRB S1=1, S0=0 S1=1, S0=1 PLL1=0, PLL0=0 fSTRB Strobe Frequency Relative to CKREF Frequency fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1, PLL0=0 PLL1=1, PLL0=1 tCPWH tCPWL tCLKT tSPWH/L CKREF DC CKREF DC LVCMOS Input Transition Time
(5)
Min.
18 5 10
Typ.
Max.
48 15 30 94.7 100 50 331/3
Unit
Serializer Input Operating Conditions fCKREF CKREF Clock Frequency (5MHz - 48MHz); MHz
% of fCKREF
T=1/fCKREF T=1/fCKREF 10-90% T=1/fCKREF
Setu p Tim e
t S TC
0.2 0.2 T x 4/12
0.5 0.5
0.8 0.8 20 T x 8/12
T T ns ns
STROBE Pulse Width HIGH/LOW DP(n) Setup to STROBE (DIRI=1, f=5MHz)
tSTC
S TR OBE D P [1:1 0] Data t HT C
2.5
ns
H old T im e
tHTC
DP(n) Hold to STROBE (DIRI=1, f=5MHz)
S TR OBE D P [1: 10] Data
2.0
ns
Serializer AC Electrical Characteristics
tTCCD STROBE
VDD/2 V
DIFF
tRCCD
=0 VDD/2
tTCCD
Transmitter Clock Input to Clock Output Delay(6)
CKSCKS+ CKP
19a+1.5
21a+6.5
ns
Note: STROBE=CKREF
DIRI=1, fCKREF=fSTRB Phase Lock Loop (PLL) AC Electrical Characteristics tTPLLS0 tTPLLD0 tTPLLD1 Serializer PLL Stabilization Time PLL Disable Time Loss of Clock PLL Power-Down Time CKREF Toggling and Stable 200 600 30.0 20.0 s s ns
Continued on the following page...
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 12
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SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
AC Electrical Characteristics (Continued)
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter
Deserializer AC Electrical Characteristics
Data Valid
CKP tPDV
Test Conditions
PWS1 fSTRB=fCKREF
Data
Min.
PWS0 0 1 0 1 6a-3 6a-3 12a-3 16a-3
Typ.
Max.
Unit
0 0 1 1
6a+3 6a+3 12a+3 16a+3 ns
tRCOL
DP [1:10]
fSTRB=fCKREF fSTRB=.5x fCKREF fSTRB=.5x fCKREF
tRCOP
CKP
50%
75%
50% 25%
tPDV
tRCOH
tRCOL
Data Valid to CKP HIGH (Rising Edge STROBE), CL=5pF
8a-3
8a+3
ns
Setup: DIRI= 0, CKSI and DS are valid signals.
S1=0,S0=1 tRFD Output Rise/Fall Time Data (20% to 80%) CL=8pF S1=1,S0=0 S1=1,S0=1 S1=0,S0=1 tRFC Output Rise/Fall Time CKP (20% to 80%) CL=8pF S1=1,S0=0 S1=1,S0=1
3 8 5 2 7 4 ns ns
Notes:
5. 6. Parameter is characterized, but not production tested. The average bit time "a" is a function of the serializer CKREF frequency; a=(1/f)/12.
Logic Timing Controls
Symbol
t PHL_DIR, tPLH_DIR tPLZ, tPHZ
Parameter
Propagation Delay DIRI to /DIRO Propagation Delay DIRI to DP
t
Test Conditions
DIRI L->H or H->L DIRI L->H or H->L
Min.
Typ.
Max.
17 25
Unit
ns ns
Deserializer Disable Time: S0 or S1 LOW to DPTri-State; DIRI=0,
DISDES
tDISDES
S1 or S0
25
ns
DP
Note: If S0(2) is transitioning, S1(1) must =0 for test to be valid.
tDISSER
Serializer Disable Time: S0 or S1 LOW to CKP HIGH
DIRI=1; S1(0) and S0(1)=H->L
25
ns
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 13
www.fairchildsemi.com
SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
Tape and Reel Specifications
MLP Embossed Tape Dimensions
T P0 D P2 E F K0 W Wc B0
Tc A0 P1 D1 User Direction of Feed
Package
5x5 6x6
A0 0.1
5.35 5.35
B0 0.1
5.35 5.35
D 0.5
1.55 1.55
D1 Min.
1.50 1.50
E 0.1
1.75 1.75
F 0.1
5.50 5.50
K0 0.1
1.40 1.40
P1 Typ.
8.00 8.00
P0 Typ.
4.00 4.00
P2 0.5
2.00 2.00
T Typ.
0.30 0.30
TC 0/05
0.07 0.07
W 0.3
12.00 12.00
WC Typ.
9.30 9.30
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C).
MLP Shipping Reel Dimensions
10 maximum Typical component cavity center line Typical component center line A0 Sketch B (Top View) 1.0mm maximum 1.0mm maximum Sketch C (Top View)
B0 10 maximum component rotation Sketch A (Side or Front Sectional View)
Component Rotation
Component Lateral Movement
Component Rotation
W2 max Measured at Hub
W1 Measured at Hub
B Min Dia C Dia D min
Dia A max
Dia N
DETAIL AA See detail AA
W3
Tape Width 8 12 16
Dia A Max. 330.0 330.0 330.0
Dim B Min. 1.5 1.5 1.5
Dia C +0.5/-0.2 13.0 13.0 13.0
Dia D Min. 20.2 20.2 20.2
Dim N Min. 178.0. 178.0. 178.0.
Dim W1 +2.0/-0 8.4 12.4 16.4
Dim W2 14.4 18.4 22.4
Dim W3 (LSL-USL) 7.9 ~ 10.4 11.9 ~ 15.4 15.9 ~ 19.4
Figure 8. MLP Tape and Reel
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 14
www.fairchildsemi.com
SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
Physical Dimensions
0.15 C 5.00
B A
5.00 (0.76)
(0.25 )
PIN #1 IDENT
5.38 MIN
0.15 C
3.37 MAX 3.86 MIN
0.80 MAX 0.10 C (0.20)
0.20MIN X4
0.08 C 0.05 0.00
SEATING PLANE
C
0.28 MAX X40
0.50TYP
E
3.70 3.50 0.45 0.35
PIN #1 IDENT
PIN #1 ID
0.50 3.70 3.50
(DATUM B)
PIN #1 ID
(DATUM A)
0.18-0.30
0.50
0.10 0.05
CAB C
NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION WHHD-4. THIS PACKAGE IS ALSO FOOTPRINT COMPATIBLE WITH WHHD-5. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. D. LAND PATTERN PER IPC SM-782. E. WIDTH REDUCED TO AVOID SOLDER BRIDGING. F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR TIE BAR PROTRUSIONS. G. DRAWING FILENAME: MKT-MLP32Arev3.
Figure 9. 32-Lead, Molded Leadless Package (MLP) Order Number
FIN210ACMLX
Operating Temperature Range
-30 to 70C
Package Description
32-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 5mm Square
Eco Status
Green
Packing Method
Tape & Reel
For Fairchild's definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 15
www.fairchildsemi.com
SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
Physical Dimensions (Continued)
Figure 10. 42-Ball, Ball Grid Array (BGA) Package Note: Click here for tape and reel specifications, available at: http://www.fairchildsemi.com/products/analog/pdf/bga42_tr.pdf Order Number
FIN210ACGFX
Operating Temperature Range
-30 to 70C
Package Description
42-Ball Ultra Small-Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5 x 4.5mm Wide, 0.5mm Ball Pitch
Eco Status
RoHS
Packing Method
Tape & Reel
For Fairchild's definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1 16 www.fairchildsemi.com
SerDesTM FIN210AC -- 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz
www.fairchildsemi.com
(c) 2009 Fairchild Semiconductor Corporation FIN210AC * Rev. 1.0.1
17

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